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Design Challenges for Low Power VLSI Circuits"Prof. Subir Kumar Sarkar, Department of Electronics and Telecommunication Engineering, Jadavpur University, Kolkata-700 032, India."

Keynote
Tremendous growth of the VLSI technology has been mainly due to progress of fabrication technology, which allowed systematic scale-down of device feature sizes and exponential growth of the integration level. Continuous device performance improvement is possible probably through a combination of device scaling, new device structure and material property improvement. Due to its small size, their potential integration level is significantly high and its low power operation solves some of the instability and reliability problems. The major challenges for design Engineers are to design new generation products, which consume minimum power, without compromising its performance or achieving minimum chip area. As we approach millennium, power dissipation has become the main design concern in many applications such as wristwatch, laptop, computers, and pace makers although early VLSI design did not consider it. The objective of such applications is minimum power for maximum battery life. Power dissipation is the greatest obstacle for Moore’s law. Modern chips consume power of which about 20% is wasted in leakage through the transistor gates. The traditional means of coping with increased power per generation has been to scale down the operating voltage of the chip but voltages are reaching limits due to thermal fluctuation effects. To save power, several tricks have been considered viz., minimize activity, glitches, effective capacitance, wire length of nodes and use of minimum possible supply voltage constrained by performance needed, design for high speed and then reduce voltage to get the desired speed.